CISES Advisory Board
Mr. Lin, Yaojian holds B.S. degree in Metal Materials & Heat Treatment from Huazhong University of Science and Technology with Honor of Outstanding Graduate, M.S. degree in Composite Materials from Shanghai Jiaotong University, and M.S. degree in Materials Science from University of Rochester, NY, United States. He once worked at Shanghai Jiaotong University, Lucent Bell Labs/Sychip, and STATS ChipPAC (Singapore), and is now VP of Corporate & GM of Technology R&D Center. He has over 20 years R&D and Technology Transfer Experience in Materials and Semiconductor Packaging development, especially in wafer level package and advanced packaging. He has hands-on experiences in end-to-end technology & product development from conceptual to high volume manufacturing in IPD, Wafer Bumping, WLCSP, eWLB/eWLCSP, 2.5D Fan-out & fcBGA, fcCSP and advanced SiP. He is the inventor/co-inventor of 200+ granted US patents in semiconductor packaging.
Profile coming soon…