Dr. Wenbiao Ruan

Ph.D, majoring in Electronics and Solid State Electronics at the Chinese Academy of Sciences, currently serving as the Director of R&D at Xiamen Yuntian Semiconductor Technology Co., Ltd., responsible for the research and development of processes such as through glass via (TGV), fanout packaging (WL-FO), wafer level packaging technology, and glass based high-frequency devices. He has successively served in SMIC., Institute of Microelectronics and Detection Technology. In 2010, he was appointed as an associate researcher at the Institute of Microelectronics, conducting research on the modeling of integrated circuit manufacturing processes and manufacturability design methodology for 65 nm and below node, and participating in and completing multiple national major special research projects. Published over 10 articles and applied for 18 patents.

Chiplet Process Integration Based on Glass Substrate and TGV Process

The hole size can be less than 15 microns, and the metal filling capacity aspect ratio can reach 10:1. It adopts high-density intermediate layer wiring, with a minimum line width and line spacing of less than 1.5um, meeting the needs of high-density interconnections such as high-performance memory and CPU. The entire packaging body uses glass as the core layer of the intermediate layer, and uses the “RDL-First” process to flip the chip onto multiple layers of RDL wiring layers to achieve electrical interconnection. Compared with TSV, it reduces parasitic capacitance and inductance effects, reduces transmission signal delay, and can be widely used in high-frequency transmission fields.