主旨: 廖德堆博士

Dr. Marvin Liao, Vice President, APTS, TSMC

Education :

• Ph.D., Materials Science, University of Texas at Arlington, USA, 1990

Experience :

• TSMC Advanced Packaging Technology and Service, 2011 ~ now
• TSMC Fab 6 Director, 2002
• Chartered Semiconductor, Singapore, 1997
• Applied Materials, USA, 1994
• SGS Thomson Microelectronics, 1990

TSMC 3DFabricTM – a 3D chip stacking and advanced packaging solution

TSMC 3DFabric is a comprehensive portfolio of wafer level integration technologies, including SoIC for 3D chip stacking and advanced packaging technologies, such as InFO and CoWoS. Complementing advanced Si technologies, 3DFabric provides a full spectrum of scalable interconnect solutions for chiplet and heterogeneous integration with system performance optimized to enable next generation products.

SoIC is a 3D chip stacking platform which offers the highest-density die-to-die interconnect scheme from copper direct bonding with sub 10 um bond pitch. This capability is what any HPC product would like to have for high bandwidth, high power efficiency, and improved SI/PI. It consists of chip-on-wafer (or CoW) and wafer-on-wafer (or WoW) stacking technologies. We have already started production on N7-on-N7 SoIC-CoW process for one of our lead HPC customers, AMD, to stack SRAM as Level 3 cache on the world’s 1st SoIC-based CPU and witnessed the significant performance gains in this data center CPU product.

InFO and CoWoS are the two advanced packaging technology platforms that can integrate SoC, SoIC, and other chips or components in various configurations. We have re-grouped our InFO technologies into three families. InFO-PoP supports advanced mobile SoC applications. InFO-2D and InFO-3D enable chiplet integration for various mobile, portable, and HPC applications. CoWoS, a 2.5D stacking technology, has three interposer technologies, one Si and two organic, to connect the chips for HPC applications that need integration of advanced logic and high-bandwidth memory or HBM. With these advanced packaging platforms, we believe we can support more performance needs with the integration of embedded DTC in the increased size of interposer. Moreover, the organic interposer technologies, will be developed to support interposer size larger than 4 reticles in the years to come.

Our newest 3DFabric fab will start production in the second half of this year.

It is a first-of-its-kind fab, designed to achieve optimal quality and cycle time performance by integrating testing, SoIC, and advanced packaging in a fully automated facility. 3DFabric ecosystem including substrate, memory, and thermal solution is also our focus. Substrate particularly is a very critical component as the interposer and substrate size grown bigger in the future. TSMC will involve in the substrate technology and supply chain and work closely with customers to address the challenges.

TSMC 3DFabric technology complements advanced logic technologies to provide a full spectrum of scalable interconnect solutions to optimize system power, performance, and area of your next generation products and innovations.